0a524f2404
* Refactor CUDA 2D transpose implementation to support multiple kernel types and improve parameter handling - Introduced a `conv2d_transpose_params` struct for better parameter management. - Updated `conv2d_transpose_kernel` to be templated for different kernel types (float and half). - Modified `ggml_cuda_conv_2d_transpose_p0` to handle both F16 and F32 kernel types. - Enhanced test cases to validate functionality for both kernel types. * Refactor test cases for 2D convolution transpose to support dynamic kernel types - Updated `test_conv_transpose_2d` structure to improve parameter handling by reordering constructor arguments. - Enhanced test case generation to iterate over kernel types, allowing for flexible testing of different configurations. - Removed hardcoded kernel type instances in favor of a loop for better maintainability and scalability. * Refactor ggml_compute_forward_conv_transpose_2d to support both F16 and F32 tensor types. * Refactor conv2d transpose kernel to use a template for kernel type, enhancing flexibility for different data types. Update test cases to include both F16 and F32 tensor types for comprehensive coverage. * Update ggml/src/ggml-cuda/conv2d-transpose.cu Co-authored-by: Aman Gupta <amangupta052@gmail.com> * Update ggml/src/ggml-cpu/ggml-cpu.c Co-authored-by: Aman Gupta <amangupta052@gmail.com> * Refactor conv2d transpose implementation by removing the conv2d_transpose_params struct and dispatching with direct kernel launch. * Enhance cpu conv2d transpose implementation by introducing a templated kernel type for improved flexibility with F16 and F32 data types. --------- Co-authored-by: Aman Gupta <amangupta052@gmail.com>
116 lines
4.7 KiB
Plaintext
116 lines
4.7 KiB
Plaintext
#include "conv2d-transpose.cuh"
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#include "convert.cuh"
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template <typename kernel_t>
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static __global__ void conv2d_transpose_kernel(const float * __restrict__ input,
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const kernel_t * __restrict__ kernel,
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float * __restrict__ output,
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const int in_w,
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const int in_h,
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const int out_w,
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const int out_h,
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const int kernel_w,
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const int kernel_h,
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const int stride,
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const int c_in,
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const int c_out,
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const int batches) {
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const int global_idx = blockIdx.x * blockDim.x + threadIdx.x;
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const int total_elements = out_w * out_h * c_out * batches;
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if (global_idx >= total_elements) {
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return;
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}
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const int out_x_idx = global_idx % out_w;
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const int out_y_idx = (global_idx / out_w) % out_h;
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const int c_idx = (global_idx / (out_w * out_h)) % c_out;
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const int n_idx = global_idx / (out_w * out_h * c_out);
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float accumulator = 0;
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// For each output idx, find the inputs that contribute to it by checking stride alignment and bounds
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for (int c_in_idx = 0; c_in_idx < c_in; c_in_idx++) {
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for (int kh = 0; kh < kernel_h; ++kh) {
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int in_y = out_y_idx - kh;
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if (in_y < 0 || in_y % stride) {
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continue;
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}
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in_y /= stride;
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if (in_y >= in_h) {
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continue;
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}
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for (int kw = 0; kw < kernel_w; ++kw) {
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int in_x = out_x_idx - kw;
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if (in_x < 0 || in_x % stride) {
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continue;
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}
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in_x /= stride;
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if (in_x >= in_w) {
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continue;
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}
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const int input_idx = (in_w * in_h * c_in) * n_idx + (in_w * in_h) * c_in_idx + (in_w) *in_y + in_x;
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const int kernel_idx =
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(kernel_h * kernel_w * c_out) * c_in_idx + (kernel_h * kernel_w) * c_idx + (kernel_w) *kh + kw;
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float input_val = input[input_idx];
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kernel_t kern_val = kernel[kernel_idx];
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accumulator += input_val * ggml_cuda_cast<float>(kern_val);
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}
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}
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}
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output[(out_w * out_h * c_out) * n_idx + (out_w * out_h) * c_idx + (out_w) *out_y_idx + out_x_idx] = accumulator;
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}
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//input is (W, H, C_in, N), Kernel is (W, H, C_out, C_in)
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void ggml_cuda_conv_2d_transpose_p0(ggml_backend_cuda_context & ctx, ggml_tensor * dst) {
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const ggml_tensor * kernel = dst->src[0];
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const ggml_tensor * input = dst->src[1];
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GGML_ASSERT(kernel->type == GGML_TYPE_F16 || kernel->type == GGML_TYPE_F32);
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GGML_ASSERT(input->type == GGML_TYPE_F32 && dst->type == GGML_TYPE_F32);
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const float * input_data = (const float *) input->data;
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float * output_data = (float *) dst->data;
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const void * kernel_data = kernel->data;
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const int input_w = input->ne[0];
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const int input_h = input->ne[1];
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const int output_w = dst->ne[0];
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const int output_h = dst->ne[1];
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const int channels_in = input->ne[2];
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const int channels_out = kernel->ne[2];
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const int kernel_w = kernel->ne[0];
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const int kernel_h = kernel->ne[1];
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const int stride = dst->op_params[0];
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const int batches = input->ne[3];
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GGML_ASSERT(channels_in == kernel->ne[3]);
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GGML_ASSERT(stride > 0);
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cudaStream_t st = ctx.stream();
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GGML_ASSERT(ggml_is_contiguous(input));
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GGML_ASSERT(ggml_is_contiguous(kernel));
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GGML_ASSERT(ggml_is_contiguous(dst));
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const int total = output_w * output_h * channels_out * batches;
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const int blocks = (total + CUDA_CONV2D_TRANSPOSE_BLOCK_SIZE - 1) / CUDA_CONV2D_TRANSPOSE_BLOCK_SIZE;
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if (kernel->type == GGML_TYPE_F16) {
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conv2d_transpose_kernel<half><<<blocks, CUDA_CONV2D_TRANSPOSE_BLOCK_SIZE, 0, st>>>(
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input_data, (const half *) kernel_data, output_data, input_w, input_h, output_w, output_h, kernel_w,
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kernel_h, stride, channels_in, channels_out, batches);
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} else {
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conv2d_transpose_kernel<float><<<blocks, CUDA_CONV2D_TRANSPOSE_BLOCK_SIZE, 0, st>>>(
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input_data, (const float *) kernel_data, output_data, input_w, input_h, output_w, output_h, kernel_w,
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kernel_h, stride, channels_in, channels_out, batches);
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}
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}
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