41a63be28e
* hexagon: allow host to set max vmem size We use a sane default but it's helpful to allow for an override if needed. * hexagon: add support for measuring vmem space and move pinned mmaping management to host * hexagon: update vmem checks to use uint64 * hexagon: bump op buffers to 16 (matches max mmaps) * hexagon: bump default vmem to 3.2GB * hexagon: add support for autodetecting vmem space and some logging cleanup in that area * hexagon: fix whitespace warnings * Update scripts/snapdragon/adb/run-cli.sh Co-authored-by: Pascal <admin@serveurperso.com> * hex-adb: fix run-completion script --------- Co-authored-by: Pascal <admin@serveurperso.com>
178 lines
5.2 KiB
C
178 lines
5.2 KiB
C
#ifndef HTP_OPS_H
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#define HTP_OPS_H
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#include <assert.h>
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// ggml-common.h must be included prio to this header
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enum htp_status {
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HTP_STATUS_OK = 1,
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HTP_STATUS_INTERNAL_ERR = 2,
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HTP_STATUS_NO_SUPPORT = 3,
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HTP_STATUS_INVAL_PARAMS = 4,
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HTP_STATUS_VTCM_TOO_SMALL = 5,
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};
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// First set of values must match the ggml_type.
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// Duplicated here because we can't include full ggml.h in the htp build.
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// We have some static_asserts in the cpp code to ensure things are in sync.
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enum htp_data_type {
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HTP_TYPE_F32 = 0,
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HTP_TYPE_F16 = 1,
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HTP_TYPE_Q4_0 = 2,
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HTP_TYPE_Q8_0 = 8,
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HTP_TYPE_IQ4_NL = 20,
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HTP_TYPE_I32 = 26,
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HTP_TYPE_I64 = 27,
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HTP_TYPE_MXFP4 = 39,
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// types used internally for repack, dyn.quant, etc
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HTP_TYPE_Q4_0x4x2 = 200,
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HTP_TYPE_Q8_0x4x2,
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HTP_TYPE_MXFP4x4x2,
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HTP_TYPE_INVALID
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};
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// Constats for internal types
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#define QK_Q4_0x4x2 256 // 4x Q4_0 blocks packed with next 4x Q4_0 blocks (size in bytes 128)
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#define QK_Q8_0x4x2 256 // 4x Q8_0 blocks concat with next 4x Q8_0 blocks
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#define QK_MXFP4x4x2 256 // 4x MXFP4 blocks concat with next 4x MXFP4 blocks
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// Mask to enable various stages of the Ops.
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// Used for debugging and profiling.
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enum htp_op_stage {
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HTP_OPSTAGE_QUEUE = (1 << 0), // Enable Queueing (ie calls into NPU)
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HTP_OPSTAGE_COMPUTE = (1 << 1), // Enable Compute
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};
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// Do not reorder first 4 (used as an index)
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enum htp_op_code {
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HTP_OP_MUL = 0,
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HTP_OP_ADD = 1,
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HTP_OP_SUB = 2,
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HTP_OP_DIV = 3,
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HTP_OP_MUL_MAT,
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HTP_OP_MUL_MAT_ID,
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HTP_OP_RMS_NORM,
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HTP_OP_UNARY_SILU,
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HTP_OP_UNARY_GELU,
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HTP_OP_UNARY_SIGMOID,
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HTP_OP_UNARY_EXP,
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HTP_OP_UNARY_NEG,
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HTP_OP_UNARY_SOFTPLUS,
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HTP_OP_GLU_SWIGLU,
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HTP_OP_GLU_SWIGLU_OAI,
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HTP_OP_GLU_GEGLU,
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HTP_OP_SOFTMAX,
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HTP_OP_ADD_ID,
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HTP_OP_ROPE,
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HTP_OP_FLASH_ATTN_EXT,
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HTP_OP_SET_ROWS,
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HTP_OP_GET_ROWS,
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HTP_OP_SCALE,
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HTP_OP_CPY,
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HTP_OP_ARGSORT,
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HTP_OP_SQR,
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HTP_OP_SQRT,
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HTP_OP_SUM_ROWS,
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HTP_OP_SSM_CONV,
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HTP_OP_REPEAT,
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HTP_OP_CUMSUM,
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HTP_OP_FILL,
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HTP_OP_DIAG,
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HTP_OP_SOLVE_TRI,
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HTP_OP_INVALID
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};
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#define HTP_OP_MAX_DIMS 4 // aka GGML_MAX_DIMS
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#define HTP_OP_MAX_INPUTS 6 // aka GGML_MAX_SRCS
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#define HTP_OP_MAX_PARAMS 16 // aka GGML_MAX_OP_PARAMS
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#define HTP_OP_MAX_BUFS 16
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#define HTP_OP_MAX_REQS 256
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#define HTP_OP_MAX_TENSORS (HTP_OP_MAX_REQS * HTP_OP_MAX_INPUTS + HTP_OP_MAX_REQS)
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#define HTP_OP_MAX_VMEM_DEFAULT (3355443200u)
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#define HTP_MMAP_MAX_VMEM (2147483648u)
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enum htp_tensor_flags {
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HTP_TENSOR_COMPUTE = (1U << 0), // Tensor buffer temporal compute data (not weights)
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HTP_TENSOR_FLUSHED = (1U << 1) // Tensor buffer has been flushed (set by the NPU)
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};
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// Tensor descriptor
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struct htp_tensor {
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uint32_t data; // Buffer offset in the messages, and data pointer on the NPU
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uint32_t size; // Data size in bytes
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uint32_t flags; // Buffer / tensor flags
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uint16_t type; // Data type
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uint16_t bi; // Buffer index
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uint32_t ne[HTP_OP_MAX_DIMS]; // Number of elements
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uint32_t nb[HTP_OP_MAX_DIMS]; // Stride in bytes (see ggml.h ggml_tensor)
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};
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// Buffer descriptor
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struct htp_buf_desc {
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uint64_t base; // base address
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uint64_t size; // total size
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uint32_t flags; // buffer flags (unused)
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uint32_t fd; // file descriptor
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};
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enum htp_op_flags {
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HTP_OPFLAGS_SKIP_COMPUTE = (1U << 0), // Skip actual computation (used for profiling)
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};
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// Op descriptor
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struct htp_op_desc {
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uint32_t opcode; // GGML/HTP Op
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uint32_t flags; // Op flags
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int32_t params[HTP_OP_MAX_PARAMS]; // Params for the op, e.g. epsilon of RMS norm
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uint16_t src[HTP_OP_MAX_INPUTS]; // Input tensors indices
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uint16_t dst; // Output tensor index
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};
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enum htp_profiler_mode {
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HTP_PROF_DISABLED = 0,
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HTP_PROF_BASIC = 1,
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HTP_PROF_PMU = 2,
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};
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#define HTP_PROF_PMU_NCNT 8
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// Profile descriptor
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struct htp_prof_desc {
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uint32_t opcode; // GGML/HTP Op
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uint32_t usecs; // Number of usec
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uint32_t cycles; // Number of cycles
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uint32_t pad; // Unused
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uint32_t pmu[HTP_PROF_PMU_NCNT]; // PMU counters
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};
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struct htp_opbatch_req {
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uint32_t id; // Batch id
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uint32_t n_bufs; // Number of buffers
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uint32_t n_tensors; // Number of tensors
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uint32_t n_ops; // Number of ops
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uint32_t flags; // unused
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uint32_t pad; // unused
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// struct htp_buf_desc bufs[]; -- dspqueue buf 0
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// struct htp_tensor tensors[]; -- dspqueue buf 0
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// struct htp_op_desc ops[]; -- dspqueue buf 0
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};
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struct htp_opbatch_rsp {
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uint32_t id; // Batch id
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uint32_t status; // HTP_STATUS_...
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uint32_t n_bufs; // Number of buffers
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uint32_t n_tensors; // Number of tensors
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uint32_t n_ops; // Number of op profile descriptors
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uint32_t pad; // unused
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// struct htp_prof_desc profs[]; -- dspqueue buf 0
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};
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#endif /* HTP_OPS_H */
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