TP: fix 0-sized tensor slices, AllReduce fallback (#21808)
* TP: fix 0-sized tensor slices, AllReduce fallback * fix layer structure <-> GPU count aliasing * add missing std::fill * fix CUDA device set, max ggml ctx size
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+15
-3
@@ -77,11 +77,23 @@ struct ggml_backend_meta_split_state llama_meta_device_get_split_state(const str
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const ggml_tensor * tensor_axis_0;
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uint32_t il;
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size_t rotation;
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size_t rotation; // when assigning tensor slices, rotate how the rounding is done for more even allocation
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};
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auto get_tensor_config_impl = [&](
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const ggml_backend_meta_split_axis axis, const std::string & suffix = "", const std::string & suffix_fallback = "") -> tensor_config {
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// the layers in a tensor can be inhomogeneous, if the pattern is cleanly divided by the number of GPUs there can be aliasing effects,
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// count only the same type of previous layers to avoid this
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auto get_il_eff = [&](const size_t il){
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size_t ret = 0;
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const bool il_is_recurrent = hparams.is_recurrent(il);
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const bool il_is_swa = hparams.is_swa(il);
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for (size_t il_prev = 0; il_prev < il; il_prev++) {
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ret += hparams.is_recurrent(il_prev) == il_is_recurrent && hparams.is_swa(il_prev) == il_is_swa;
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}
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return ret;
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};
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uint32_t il;
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std::string prefix;
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size_t rotation;
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@@ -90,13 +102,13 @@ struct ggml_backend_meta_split_state llama_meta_device_get_split_state(const str
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GGML_ASSERT(length_prefix != std::string::npos);
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prefix = tensor_name.substr(0, length_prefix + 1);
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il = std::stoull(tensor_name.substr(4, length_prefix));
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rotation = il % ud->n_devices;
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rotation = get_il_eff(il) % ud->n_devices;
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} else if (tensor_name.substr(0, 6) == "cache_") {
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const size_t layer_index_start = tensor_name.find("_l", 6);
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GGML_ASSERT(layer_index_start != std::string::npos);
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il = std::stoull(tensor_name.substr(layer_index_start + 2));
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prefix = "blk." + std::to_string(il) + ".";
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rotation = il % ud->n_devices;
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rotation = get_il_eff(il) % ud->n_devices;
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} else {
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il = 0;
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rotation = hparams.n_layer % ud->n_devices;
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